1. Field of the Invention
The present invention relates to a grand alliance (GA) HDTV receiver using a vestigial sideband (VSB) modulation transmission system, and more particularly, to a digital frequency phase locked loop (FPLL) for a transmission system which can linearly change frequency band phase characteristics by digitally implementing the same in the FPLL of the VSB receiver. Among various transmission systems for GA, an 8 VSB method was developed through various experiments.
2. Discussion of the Related Art
In conventional methods of attenuating only one sideband signal among two sidebands occurring in upper and lower portions of a carrier when a signal is amplitude-modulated, the VSB method also modulates the remaining signal. This causes the band efficiency of a double sideband method using upper and lower sidebands to decrease. To overcome this problem, a single sideband method using only one sideband was developed in the VSB for filter implementation.
Moreover, the VSB method, which is an AM modulation method, has been used by video-related art technicians as a video processing technology.
The above-mentioned 8 VSB has 8 levels of a transmitted signal and adopts a VSB modulation method for releasing the signal as an atmospheric wave. If digital data is modulated into 8 VSB and released to the air via an antenna in a broadcasting station, the broadcasting program can be viewed in homes by receiving the released signal in a HDTV receiver and demodulating the received signal. However, when VSB modulation is executed in the broadcasting station, the signal is released to the air together with a pilot signal for precise demodulation.
Since the frequency for HDTV broadcasting is the same as that for the current NTSC (National Television System Committee) TV broadcasting, the pilot signal should have a very small value to prevent the NTSC broadcasting from being affected by the HDTV broadcasting frequency. For example, if the interval of adjacent two signal levels among 8 levels of the 8 VSB is 2, the magnitude of the pilot signal is 1.25, and the power of a transmission signal is set to be increased by 0.3 dB.
FIG. 1 is a block diagram of a conventional HDTV receiver. A general transmission system will now be described.
Referring to FIG. 1, the conventional HDTV receiver includes a frequency synthesizer 2 for receiving a channel signal and for generating and outputting a first local frequency (1st LO). A first mixer 3 multiplies a broadcasting signal input via an antenna 1 with the first local frequency and outputs the frequency of a desired broadcasting signal. Band pass filter (BPF) 4 filters only the components of the desired broadcasting signal from the output signal of the first mixer 3 and eliminates the remaining components. Second mixer 5 multiplies a second local frequency (2nd LO) output from a VCO 6 (to be described later) with the output of the BPF 4, which is the frequency of the desired broadcasting signal. Surface acoustic wave (SAW) filter 7 removes the section except for the information-containing bands from the output of the second mixer 5, and an intermediate frequency (IF) amplifier 8 converts the signal output from the SAW filter 7 into an intermediate frequency and amplifies the same. Phase delay 12 phase-delays by 90.degree. the output signal of a third local oscillator 11, whose center frequency is fixed. Third mixer 9 multiplies the output signal of the third local oscillator 11 with the signal amplified by the IF amplifier 8 to output an I-channel signal. Fourth mixer 10 multiplies the signal whose center frequency is a fixed output from the third local oscillator 11 with the signal amplified by the IF amplifier 8 to output a Q-channel signal. Automatic frequency control (AFC) filter 13 having a second manual filter for shifting the frequency of the I-channel signal into a phase. Limiter 14 measures the symbol of the output signal of the AFC filter 13, and a fifth mixer 15 multiplies the Q-channel signal of the fourth mixer 10 with the output signal of the limiter 14 and outputs the multiplication result. Automatic phase control (APC) filter 16 restricts the band of the output signal of the fifth mixer 15, and a voltage-controlled oscillator (VCO) 6 outputs the second local frequency (2nd LO) to the second mixer 5 by the control of the output signal of the APC filter 16.
The operation of the above-described configuration will now be explained.
The broadcasting signal, which is in the air, is input to the receiver via the antenna 1. The frequency synthesizer 2 receives a user's selected channel signal and generates a first local frequency signal having 920 MHz of frequency difference from a desired broadcasting signal so that the output of the first mixer 3 is 920 MHz.
The first mixer 3 multiplies the outputs of the antenna 1 and frequency synthesizer 2 so that the frequency of the desired broadcasting signal among signals input via the antenna 1 are 920 MHz Since the center frequency of the BPF 4, having received the output signal of the first mixer 3, is set as 920 MHz only the desired broadcasting signal components are filtered. The remaining components are eliminated.
The second mixer 5 multiplies the second local frequency input from the VCO 6 with the output of the BPF 4 to lower the frequency of the desired broadcasting signal to 44 MHz.
Since all kinds of information are present in the bands ranging from the intermediate frequency of 44 MHz of a HDTV broadcasting signal to 6 MHz, the SAW filter 7 eliminates the remaining section, excluding the information-containing band (6 MHz) from the output of the second mixer 5. The output of the SAW filter 7 is amplified in the IF amplifier 8 and is then input to the third and fourth mixers, 9 and 10 respectively.
The output of the third local oscillator 11, whose center frequency is set to 44 MHz, is input to the fourth mixer 10 and is multiplied with the output of the IF amplifier 8 to generate a Q-channel signal. Also, the output of the third local oscillator 11 is phase-delayed in the 90.degree.-phase delay 12, and is then input to the third mixer 9.
The phase-delayed signal is multiplied with the output signal of the IF amplifier 8 to generate an I-channel signal.
The frequency of the pilot signal inserted in the broadcasting station should exist exactly at 44 MHz from the output of the IF amplifier 8 for normal operation of the remaining receiver sides. However, the frequency does not often exist exactly in 44 MHz. Thus, since the output frequency of the third local oscillator 11 is set to 44 MHz, the beat corresponding to the frequency difference exists in the outputs of the third and fourth mixers if the output frequency of the pilot signal is not 44 HMz in the IF amplifier 8.
In order to remove the beat frequency, a frequency phase locked loop (FPLL) is adopted, with the following configuration. Assuming that the output frequency of the I-channel signal output from the third mixer 9 is Wo and that of the pilot signal of the IF amplifier 8 is Wi, Cos (Wi-Wo) t=Cos .DELTA.Wt, where .DELTA.W=Wo-Wi (beat frequency). On the other hand, the Q-channel signal output from the fourth mixer 10 has a format of Sin .DELTA.Wt.
The AFC filter 13 is composed of a second manual filter capable of locking the beat frequency of .+-.100 KHz. Also, the output of the AFC filter 13 has characteristics of changing the frequency into the phase, as well as the characteristic of being a lowpass filter (LPF). Thus, the AFC filter 13 generates output values as indicated in a frequency-versus-phase characteristic graph of FIG. 2 with respect to the respective beat frequencies of the I-channel signal. The output of the AFC filter 13 is input to the limiter 14 for measuring the signal symbol. The output of the limiter 14 is multiplied with the Q-channel signal in the fifth mixer 15 to be output as in the output characteristic graph of FIG. 3.
The output of the fifth mixer 15 is 2 KHz and passes through the APC filter 16, which restricts the signal band to control the VCO 6.
When the beat frequency is present and causes the output of the limiter 14 to change, the frequency locked loop (FLL) process is executed. When the FLL process is terminated and the output of the limiter 14 is no longer changed, a phase locked loop (PLL) for correcting the phase begins. This is shown in the graph of FIG. 4 for the FPLL process.
An analog FPLL process of the 8 VSB receiver adopted in the GA will now be described with reference to accompanying drawings.
FIG. 5 is a block diagram of a conventional analog FPLL. Referring to FIG. 5, the conventional analog FPLL includes a phase delay 12 whose center frequency is fixed by 90.degree. for phase-delaying the output frequency of a third oscillator 11. A third mixer 9 multiples the phase-delayed signal output from the third oscillator 11 with the signal amplified by the IF amplifier 8 shown in FIG. 1. First lowpass filter (LPF) 17 eliminates high-frequency components, except for a bit-frequency from the output of the third mixer 9. First A/D converter 18 samples the output signal of the first LPF 17 in a symbol frequency. First NTSC carrier eliminating filter 19 eliminates interferences of NTSC adjacent channel of the digital data sampled by the first A/D converter 18, and a first D/A converter 20 converts the digital signal output from the first NTSC carrier eliminating filter 19 into an analog signal. Third LPF 21 eliminates components of the analog signal, and an AFC filter 13 converts the frequency of the signal into a phase. Limiter 14 measures the symbol of the output signal of the AFC filter 13. Fourth mixer 10 multiplies the signal amplified by the IF amplifier 8 with the output signal of the third local oscillator 11, and a third LPF 22 eliminates high-frequency components excluding a bit-frequency from the output of the fourth mixer 10. Second A/D converter 23 samples the output signal of the second LPF 22 in a symbol frequency. Second NTSC carrier eliminating filter 24 eliminates interferences of NTSC adjacent channel of the digital data sampled by the second A/D converter 23, and a second D/A converter 25 converts the digital signal output from the second NTSC carrier eliminating filter 24 into an analog signal. Fourth LPF 26 eliminates high-frequency components of the analog signal output from the second D/A converter 25, and a fifth mixer 15 multiples the output of the fourth LPF 26 with the output of the limiter 14. APC filter 16 limits the band of the output signal of the fifth mixer 15.
The operation of the conventional analog FPLL will now be described, with reference to FIG. 5. The output of the third local oscillator 11 is input to the fourth mixer 10 and 90.degree.-phase delay 12. The third mixer 9, as shown in FIG. 1, multiplies the signal amplified in the IF amplifier 8 with the 90.degree.-phase-delayed signal of the output signal of the third local oscillator 11. The fourth mixer 10 multiplies the amplified signal with the output signal of the third local oscillator 11 and then outputs the multiplication result.
The output signal of the fourth mixer 10 eliminates the high-frequency components, excluding the bit-frequency from the first and second LPFs 17 and 22. The first and second A/D converters 18 and 23 sample the output signals of the first and second LPFs 17 and 22 in a symbol frequency. In order to eliminate the interference of NTSC adjacent channels from the sampled digital signals, the first and second NTSC carrier eliminating filters 19 and 24 are used.
The first and second DIA converters 20 and 25 convert the digital signals into analog signals and then the high-frequency components thereof are eliminated by the third and fourth LPFs 21 and 26. The output signal of the third LPF 21, functioning as an LPF, converts from its frequency into a phase through the AFC filter 13. The limiter 14 measures the symbol of the output signal of the AFC filter 13. The output signal of the limiter 14 and that of the fourth LPF 26 are multiplied in the fifth mixer 15 to then be passed through the APC filter 16 for limiting the band of a 2 KHz signal to control the VCO 6.
The conventional FPLL is an analog construction. Therefore, the results are non-linear frequency-versus-phase characteristics in the FPLL processing. Moreover, because the respective elements are of an analog construction, the hardware is bulky.